see also Quad Delta-Sigma Board
Or that external article: on mbed.org

The laodcell was connected with a 6-wire configuration to the evaluation board of the AD7190.
The samplerate was set to 10 S/s, chopping enabled (continuous offset and gain correction). The analog 5V supply was powered from the RIGOL DP832, which has a very low noise level.

We measured an astonishing low noise level of about 50nV(rms).

Here we evaluated the possibility to use a loudspeaker as a low-frequency microphone. Due to lack of shielding of electromagnetic fields, the coil picks up a huge amount of signals, which are not related to acoustic sound waves.

ad7190_bridge.zip

When the LSBit is zero, that is transferred from the ADC to the MCU, the MCU reads a one.

Since the DOUT signal of the ADCs SPI is also used to signal data ready (active low), DOUT goes immediately high at the last rising edge of SCLK.
The rising edge of SCLK and DOUT happens nearly simultaneously. The DOUT (MISO) line is sampled by the MCU at the rising edge of SCLK. So this signal is not in a steady state, when the sampling occurs. In my setup with the Arduino DUE, the LSBit is allways read as one.

Image based on this from Wikipedia, created by Cburnett.

• As a workaround perhaps a 2nd order RC-lowpass filter could help to implement a small phase shift. With 2x 1kΩ and 2x 100pF we get a delay of about 100ns (0.2 x VCC threshold), and the signal integrity is guaranteed until 500kHz of clock frequency.
  
• Another possibility would be a software implementation of the SPI on the master side, which would sample the MISO line just before rising the clock line.